About this course

What you'll learn

Gain exposure to industry standard

FPGA Signal Processing Implementation Flow.

Understanding Different DSP Algorithms

To gain an Understanding of RTL coding for DSP algorithms .

To gain knowledge on Xilinx System Generator

Write Verilog test fixtures for simulation

Students are required to have basic knowledge on the following topics:

Digital Signal Processing Algorithm Basics.

Knowledge on HDL and FPGA.

Tools and Resources used

Xilinx ISE

Xilinx System Generator

MATLAB-SIMULINK

Modelsim

SPARTAN FPGA Evaluation Kit

Take away

Write RTL Verilog code for DSP algorithm Like Digital Filters, FFT etc.

Understanding Parallel and pipelined processing concepts

Digital Image Processing

Write Verilog test fixtures for simulation

Introduction to DSP

History of DSP

Representation of DSP Algorithms

Understanding Digital Filters.

Understanding FFT.

Parallel Processing concepts.

Pipelined Processing concepts.

Arithmetic for DSP

Number formats

Image Processing and Cryptography

Image Processing concepts

AES Algorithm

XIlxin DSP system Geenrator

Introduction to System generator

Building DSP systems

Integrating HDL into System generator.

Generating Netlist from System generator

FPGA with system generator

LAB Exercises: Note@

Hands-on Labs Sessions are possible only if:
Individual PCs pre-loaded with Xilinx ISE and Modelsim.

Lab Exercises on SPARTAN FPGA Evaluation Kit

Note:There will be assignments on every Module and enough hands on will be given with strong programming knowledge.