About this course

What you'll learn

Have fairly strong fundamentals in HDL Coding.

Gain exposure to industry standard FPGA Implementation Flow.

Understanding Different Coding Methodologies

To gain an Understanding of RTL coding for synthesis

Write Verilog test fixtures for simulation

Students are required to have basic knowledge on the following topics:

Digital electronics/ Logic Design Basics

Tools and Resources used

Xilinx ISE/Vivado for synthesis

Modelsim for simulation

SPARTAN FPGA Evaluation Kit

Take away

Write RTL Verilog code for synthesis

Write Verilog test fixtures for simulation

Create a Finite State Machine (FSM) by using Verilog

Target and optimize Xilinx FPGAs by using Verilog

Use enhanced Verilog file I/O capability

Run a timing simulation by using Xilinx Simprim libraries

To Run Behavioral,Post Map,Post Route and Place Route simulations

Xilinx and Modelsim Took knowledge

Download to the evaluation demo board

Programming in Verilog

History of Verilog

Operators in verilog

Design styles in verilog

Implementation of combinational circuits using verilog

Implementation of sequential circuits using verilog

Design of FSM using verilog

Memory modeling and FSM

Design of memory using RTL coding

Design of FSM for complex sequential circuits

Different types of memory design Case study

Design of Test Benches

Introduction to Test benches

Implementation of test benches for combinational circuits

Implementation of test benches for sequential circuits

Tasks and Functions and directives

Introduction to tasks

Introduction to functions

Difference between task and function

RTL coding for efficient synthesis

System task and functions

User defined primitives

Combinational Circuit Design

Adders

Mux/Demux

Encoder/Decoders

Multipliers

Sequential Circuit Design

Flip Flop's

Counters

CRC

Shift registers

Serial to Parallel Convertors

IP Core Design

DCM/PLL Design

FIFO Design

Hardware Synthesis using Xilinx/Vivado

Industry FPGA implementation Flow

Schematic Creation

Hardware synthesis

Timing Simulations

FPGA

Introduction to FPGA

FPGA basic Architecture.

FPGA Programming with Verilog.

Tool Training

Practical Lab example: FIFO, Filter