About this course

What you'll learn

This technical training course provides training on Xilinx System DSP Generator.

This course is a thorough introduction to the DSP Design Flow using MATLAB Simulink/Xilinx System Generator.

It also covers Generation of Verilog/VHDL from Net list system generator block.

This course combines Theory with practical lab exercises to reinforce key concepts.

The course is designed for engineers who are already having sound knowledge on Digital Electronics/Logic Design, Knowledge of Verilog HDL and FPGA DSP concepts MATLAB-SIMULNK Tool Basics.

To gain an Understanding MATLAB- SIMULINK and Xilinx System Generator Tool Flow.

Build Design Blocks for simulation Create a Finite State Machine (FSM) by using Xilinx System Generator.

Target and optimize Xilinx FPGAs by using Xilinx System Generator To Do HDL-Co simulation Download to the evaluation demoboard

MATLAB Introduction

Simulink Introduction

Designing with Simulink

Building Blocks in Simulink

Explore the Simulink interface and block libraries

Creating and editing a simple Simulink model

Defining system inputs and outputs

Simulating the model and analyzing results

Designing filters in Simulink

Converting filters to fixed point

Design Creation Basics

Basic concepts of creating a design using System Generator

Basics of building a design in System Generator

Simulate a design in System Generator

Run the System Generator token to generate a Xilinx FPGA bit stream

Create a subsystem

Improve performance using dedicated Xilinx FPGA math functions

Signal Routing

Understanding how signal routing blocks can be used redefine or modify a fixed-point number at the bit level Convert a fixed-point number into a new fixed-point number Slice bits from a fixed-point number Pad and Unpad a fixed-point number

System Control

Create a finite state machine using the Mcode block in System Generator

Creating FSM using Inbuilt sys gen block

Multi Rate systems

Sample rates in a DSP System

Up Sampling

Down Sampling

Convert a serial stream of data to a parallel word

Convert a parallel word of data into a serial stream

Memory Design

Using a Xilinx ROM block to implement a LUT-based operation block or distributed RAM

Use a Xilinx ROM block to implement a trig or math function such as arcsin

Filter Design

Use the Matlab FDA tool to generate and set the filter coefficients

Use the Xilinx FIR Compiler to generate various filter implementations

Modulation Demodulation Design

BPSK Mod demod design

QPSK Design

FSK Design

ASK Design