About Day_wise_FPGA_VIVADO_SYSGEN1 course
What you'll learn
FPGA
Introduction to FPGA
FPGA basic Architecture
Xilinx and FPGA Architecture
FPGA Internal resource
FPGA Design Essentials
FPGA Architecture Overview
FPGA Input/output Blocks(IOBs)
Special FPGA functions
Logic Synthesis
FPGA Programming with Verilog.
Tool Training
Programming in Verilog HDL/VHDL
History of Verilog HDL/VHDL
Overview of HDLs
Verilog/VHDL
Operators in Verilog
Design styles in Verilog
Programming in Verilog HDL/VHDL
Implementation of combinational circuits using Verilog
Implementation of sequential circuits using Verilog
Design of FSM using Verilog, Mealy and Moore Machine
Memory modelling and FSM
Design of memory using RTL coding
Design of FSM for complex sequential circuits
Different types of memory design
Design of Test Benches
Introduction to Test benches
Implementation of test benches for combinational circuits
Implementation of test benches for sequential circuits
Tasks and Functions and directives
Introduction to tasks
Introduction to functions
Difference between task and function
IP Integration using Xilinx
Integrating IP Cores
Integrating IPs like DCM,FIFO
Coding Optimization for synthesis
RTL coding for efficient synthesis
Coding for Timing
Coding for Area
System task and functions
Case study
Vivado Tool Flow
Tool Flow basics and Understanding
Vivado Tool Flow
IO pin planning
IP FLOW
Software Development Design with C
Timing Analysis
Applying constraints and viewing reports
Clock Constrains
Reset Constrains
FPGA Resources for DSP application
Hand on FPGA Board
MATLAB and SIMULINK
Introduction to MATLAB
Data and data flow in MATLAB
Editing and debugging m files
Programming
Flow Control Conditional Statements
Error Handling Work with Multidimensional Array Cell Array & Characters Developing User Defined Function Scripts and Other functions
MATLAB Image and Video Processing
Simulink
Communication toolbox, DSP tool box
Image processing toolboxes
Getting Started with System Generator for DSP
DSP Number system Format
Fixed Point Format Q format and IEEE floating point format
Designing with Simulink
Building Blocks in Simulink
Explore the Simulink interface and block libraries
Creating and editing a simple Simulink model
Defining system inputs and outputs
Simulating the model and analysing results
Designing filters in Simulink
Converting filters to fixed point
System Generator Part 1
Design Creation Basics
Basic concepts of creating a design using System Generator
Basics of building a design in System Generator
Simulate a design in System Generator
Run the System Generator token to generate a Xilinx FPGA bit stream
Create a subsystem
Improve performance using dedicated Xilinx FPGA math functions
System Generator Part 1
Signal Routing
Understanding how signal routing blocks can be used redefine or modify a fixed-point number at the bit level
Convert a fixed-point number into a new fixed-point number
Slice bits from a fixed-point number
Pad and Unpad a fixed-point number
System Control
Create a finite state machine using the Mcode block in System Generator
Creating FSM using inbuilt sys gen block
System Generator Part 2
Multi Rate systems
Sample rates in a DSP System
Up Sampling
Down Sampling
Convert a serial stream of data to a parallel word
Convert a parallel word of data into a serial stream
Memory Design
Using a Xilinx ROM block to implement a LUT-based operation
Block or distributed RAM
Use a Xilinx ROM block to implement a trig or math function such as arcsin
Filter Design
Use the Matlab FDA tool to generate and set the filter coefficients
Use the Xilinx FIR Compiler to generate various filter implementations
Modulation Demodulation Design
BPSK Mod demod design
QPSK Design
FSK Design
ASK Design
JavaScript
Script tag
A Taste of JavaScript
No script tag