About this course

What you'll learn

VHDL Basics Review

The shape of VHDL

Demo: Multiplexer

Data Types

Concurrent Operations

Processes and Variables

Different types of VHDL Design

Designing Combinational Circuits

Designing Sequential Circuits

Introduction to Test benches

Creating memory (RAM/ROM)

FSM Design

Using Loops


Coding State Machines

Writing a Good test bench

Synthesis vs Simulation

Writing synthesisable VHDL Codes

Best Practise for RTL design

Designing with IP

Improving logic utilisation and performance

Writing parameterized code

Overview of FPGA tools(Vivado/Quartus)

Overview of FPGA debugging tools(Vivado/Quartus)

Timing Analysis basics

General concept of embedded processor in FPGA

General concept of memory and its interface option in FPGA