Training

Digital electronics/ Logic Design Basics

Xilinx ISE/Vivado for synthesis

Modelsim for simulation

SPARTAN FPGA Evaluation Kit

Write RTL Verilog code for synthesis

Write Verilog test fixtures for simulation

Create a Finite State Machine (FSM) by using Verilog

Target and optimize Xilinx FPGAs by using Verilog

Use enhanced Verilog file I/O capability

Run a timing simulation by using Xilinx Simprim libraries

To Run Behavioral,Post Map,Post Route and Place Route simulations

Xilinx and Modelsim Took knowledge

Download to the evaluation demo board

History of Verilog

Operators in verilog

Design styles in verilog

Implementation of combinational circuits using verilog

Implementation of sequential circuits using verilog

Design of FSM using verilog

Design of memory using RTL coding

Design of FSM for complex sequential circuits

Different types of memory design Case study

Introduction to Test benches

Implementation of test benches for combinational circuits

Implementation of test benches for sequential circuits

Introduction to tasks

Introduction to functions

Difference between task and function

RTL coding for efficient synthesis

System task and functions

User defined primitives

Adders

Mux/Demux

Encoder/Decoders

Multipliers

Flip Flop's

Counters

CRC

Shift registers

Serial to Parallel Convertors

DCM/PLL Design

FIFO Design

Industry FPGA implementation Flow

Schematic Creation

Hardware synthesis

Timing Simulations

Introduction to FPGA

FPGA basic Architecture.

FPGA Programming with Verilog.

Tool Training

Practical Lab example: FIFO, Filter